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RTL design manager（ASIC）
Qualifications
1、Bachelor degree with at least 5 years working experience or master degree with at least 3 years working experience
2、Major in Electronics, Information Engineering, communications, computer, automation, or related field
3、Familiarize yourself with system Verilog and UVM Validation Techniques
4、Rich experience in the design process and construction of UVM test vectors
5、 Experience in RSIC processor design plus
6、Familiar with large-scale UVM verification platform construction experience, more than 3 complete project experience
Description of responsibilities
1、 Build the validation environment and test engineer for UVM Testbench validation and testing
2、 Write detailed design documentation for Testbench, provide test documentation and test scenarios
3、 Build test engineers perform chip testing, and analyze chip problems.
4、 Complete digital circuit synthesis, layout and routing, timing analysis, consistency checking and other work
5、 Development and automation of Test flow
6、 Participate in SOC architecture, performance, and Power Evaluation
7、 Classification and debugging of bugs
8、 Diagnosis and resolution of pre-silicon and post-silicon problems
Competency Requiremen
1、RTL/digital circuit design, synthesis and simulation/verification
2、Build and debug the UVM verification platform
3、Familiarize yourself with the Testbench Hierarchical development process
4、Experience debugging modules such as UMM Driver, Monitor, Reference Model and Soreboard
5、Generate test patterns, regression tests, and statistical analysis of coverage
6、Comparison and improvement of automation results
